8-bit AVR Microcontroller with 1К Byte Flash ATtiny15L

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When PB5 is used as External Reset pin, the values in the corresponding DDRB and PORTB bit are ignored. The Port B Data Register – PORTB The Port B Data Direction Register – DDRB Bit 7 6 5 4 3 2 1 0 $18 – – – PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R R R R/W R/WS R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $17 – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PORTB DDRB 51 1187F–AVR–06/05 The Port B Input Pins Address – PINB Bit 7 6 5 4 3 2 1 0 $16 – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Read/Write R R R R R R R R Initial Value 0 0 N/A N/A N/A N/A N/A N/A PINB The Port B Input Pins address (PINB) is not a register, and this address enables access to the physical value on each Port B pin.

0 0 0 1 CK*16 (=PCK) 0 0 1 0 CK*8 (=PCK/2) 0 0 1 1 CK*4 (=PCK/4) 0 1 0 0 CK*2 (=PCK/8) 0 1 0 1 CK 0 1 1 0 CK/2 0 1 1 1 CK/4 1 0 0 0 CK/8 1 0 0 1 CK/16 1 0 1 0 CK/32 1 0 1 1 CK/64 1 1 0 0 CK/128 1 1 0 1 CK/256 1 1 1 0 CK/512 1 1 1 1 CK/1024 The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes are scaled directly from the CK oscillator clock. The Timer/Counter1 – TCNT1 Bit 7 $2F MSB 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB TCNT1 This 8-bit register contains the value of Timer/Counter1.

3. Write new EEPROM data to EEDR (optional). 4. Write a logical “1” to the EEMWE bit in EECR. 5. Within four clock cycles after setting EEMWE, write a logical “1” to EEWE. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during the four last steps to avoid these problems.

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