64.VLSI Systems by John G. Webster (Editor)

By John G. Webster (Editor)

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In order to design these clock nets to be less sensitive to process variations, Pullela et al. (108–110) have developed an automated layout algorithm that widens the clock nets rather than lengthens them while equalizing the line delays. These nets are therefore less sensitive to both under- and over-etching during the metal-patterning process. By widening the clock lines, the interconnect resistance is decreased; however, the interconnect capacitance increases. It is interesting to note that increasing the line width of those branches closer to the root of the RC tree has a greater effect on the clock path delay than increasing the widths closer to the leaf nodes (the clocked registers).

An important observation is that the accuracy required to calculate delay differences (as in clock skew) is much greater than that required when calculating absolute delay values (as in the delay of a clock path). Design of Low-Power Clock Distribution Networks (68–70) In a modern VLSI system, the clock distribution network may drive thousands of registers, creating a large capacitive load that must be efficiently sourced. Furthermore, each transition of the clock signal changes the state of each capacitive node within the clock distribution network, in contrast with the switching activity in combinational logic blocks, where the change of logic state is dependent on the logic function.

By selecting a value of clock skew toward the center of the permissible range, the tolerance of the local data path to process parameter and environmental delay variations is improved. Furthermore, this decreased sensitivity to process parameter variations by exploiting the localized permissible range of each local data path is completely compatible with the design techniques described in the following subsection. Design of Process-Insensitive Clock Distribution Networks A primary disadvantage of clock distribution networks is that the delay of each of the elements of a clock path, the distributed buffers and the interconnect impedances, are highly sensitive to geometric, material, and environmental variations that exist in an implementing technology.

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